16 April 2019
TSMC has quietly introduced a performance-enhanced version of its 7nm DUV (N7) and 5nm EUV (N5) manufacturing process. The new versions are dubbed as N7P and the N5P technologies and they consume a slightly lower amount of power and are faster compared to their predecessors.
The new process technology is already available to TSMC customers but the contract maker hasn’t announced it broadly or made a shout out to advertise to others. The performance-enhanced process, as the name implies have been designed for the TSMC clients that need ~ 18~20% higher transistor density.
The new N7P version of manufacturing process uses the same design rules but features some optimizations that help it boost performance by 7% at the same power or lower power consumption by 10% at the same clocks. This will help TSMC clients to help their chips’ overall performance.
Coming to the next major node which is the N5 based on 5nm process will soon arrive and its performance-enhanced version N5P will also arrive with the same FEOL and MOL optimizations that are available with the N7P process technology. In N5P, these optimizations will reduce consumption by 15% at the same clocks.
The N7P process has already entered mass production in the last quarter (Q2 2019) and the N5P is expected to arrive by early 2021.